1. Field of the Invention
The present invention relates to an SAR ADC (Successive Approximation Register Analog-to-Digital Converter), especially to an SAR ADC capable of minimizing energy consumption.
2. Description of the Related Art
As portable electronic products have evolved vigorously, low power consumption—capable of prolonging the battery life—has become a key issue in the design of electronic products; and among the varieties of analog-to-digital converters, the SAR ADC has been widely used in electronic products due to its power saving advantage—its analog-to-digital conversion is implemented by a simple architecture including only a comparator and few components.
Please refer to FIG. 1, which illustrates the block diagram of a prior art N-bit SAR ADC. As illustrated in FIG. 1, the SAR ADC includes a bit value determination unit 100, and a successive approximation register 140, wherein the bit value determination unit 100 includes a sample and hold circuit 110, a digital-to-analog conversion circuit 120, and a comparator 130.
The sample and hold circuit 110 is used for performing a sample and hold operation on an analog input signal VA to generate a sampled signal VA1 during a sampling stage.
The digital-to-analog conversion circuit 120, biased between a reference voltage VREF and a ground voltage VGND, is used for generating a quantization voltage VA2 according to switch control signals SWN . . . SW1.
The comparator 130 is used for comparing the sampled signal VA1 with the quantization voltage VA2 to generate a bit output B.
The successive approximation register 140 is used for successively changing the content of the switch control signals SWN . . . SW1 during a voltage comparison stage to vary the quantization voltage VA2, and successively receiving the bit output B to generate a digital output code DOUT.
During the voltage comparison stage, first, the successive approximation register 140 will output a prediction code through the switch control signals SWN . . . SW1 to cause a charging or discharging process happening in the digital-to-analog conversion circuit 120, so as to generate a corresponding level for the quantization voltage VA2. Second, the comparator 130 will compare the sampled voltage VA1 with the quantization voltage VA2, and thereby determine the content of the bit output B—“0” or “1”. Third, the successive approximation register 140 will store the bit output B in a register, and output a next prediction code according to the content of the bit output B to determine the next content of the bit output B. By repeating the three steps N times, an N bits content of the digital output code DOUT corresponding to the sampled signal VA1 will be generated.
In the process of generating the digital output code DOUT, the quantization voltage VA2 generated by the digital-to-analog conversion circuit 120 will successively approach the sampled signal VA1 in a binary-weighted manner; that is, an N bits SAR ADC will generate N values of the quantization voltage VA2—let them labeled as VA2(1), VA2(2), VA2(3), . . . , VA2(N) respectively, and the voltage difference between VA2(k) and VA2(k-1) will be half of the voltage difference between VA2(k-1) and VA2(k-2), wherein k=3 to N.
As the digital-to-analog conversion circuit 120 normally uses a plurality of switches to control the charging or discharging of a plurality of capacitors of different weightings, therefore, most energy will be dissipated in the charging or discharging of the capacitors.
For the architecture of general digital-to-analog conversion circuits, please refer to FIG. 2, which illustrates the block diagram of a prior art bit value determination unit including a digital-to-analog conversion circuit. As illustrated in FIG. 2, the prior art bit value determination unit includes a switch unit 210, a digital-to-analog conversion circuit 220, and a comparator 230, wherein the digital-to-analog conversion circuit 220 has a first capacitor array 221, a second capacitor array 222, a voltage selecting circuit 223, and a voltage selecting circuit 224.
The switch unit 210 has a pair of sampling switches, of which one side has a first contact and a second contact, and both the first contact and the second contact are coupled to a reference voltage VREF; and the other side has a third contact and a fourth contact coupled to the first capacitor array 221 and the second capacitor array 222 respectively.
The first capacitor array 221 and the second capacitor array 222 both have N+1 capacitors, with capacitances of C, C, 2C, 4C, 8C, . . . , 2N-1C respectively. The N+1 capacitors of the first capacitor array 221 has a common terminal coupled to the third contact of the switch unit 210, and N+1 bias contacts coupled to the voltage selecting circuit 223. The N+1 capacitors of the second capacitor array 222 has a common terminal coupled to the fourth contact of the switch unit 210, and N+1 bias contacts coupled to the voltage selecting circuit 224.
The voltage selecting circuit 223 is used for outputting N+1 bias voltages for the N+1 bias contacts of the first capacitor array 221 according to switch control signals SWN . . . SW1, wherein, each of the bias voltages outputted by the voltage selecting circuit 223 is selected from a group consisting of a negative analog input voltage VAN, the reference voltage VREF, and a ground voltage VGND. The voltage selecting circuit 224 is used for outputting N+1 bias voltages for the N+1 bias contacts of the second capacitor array 222 according to the switch control signals SWN . . . SW1, wherein, each of the bias voltages outputted by the voltage selecting circuit 224 is selected from a group consisting of a positive analog input voltage VAP, the reference voltage VREF, and the ground voltage VGND.
The comparator 230 has a positive input end, a negative input end, and an output end, wherein the positive input end is coupled to the third contact of the switch unit 210, and the negative input end is coupled to the fourth contact of the switch unit 210. The comparator 230 is used for generating a bit output B according to the voltage difference between the positive input end and the negative input end—the voltage difference can be expressed as VAP−VAN−γVREF, wherein 0≦γ<1. When VAP−VAN−γVREF>0, B=1; and when VAP−VAN−γVREF<0, B=0.
Please refer to FIG. 3, which illustrates a circuit of the prior art bit value determination unit of FIG. 2 formed in a sampling stage. As illustrated in FIG. 3, when in the sampling stage, both the common contact of the first capacitor array 221 and the common contact of the second capacitor array 222 are coupled to VREF, the N+1 bias contacts of the first capacitor array 221 are coupled to the negative analog input voltage VAN, and the N+1 bias contacts of the second capacitor array 222 are coupled to the positive analog input voltage VAP. By the end of the sampling stage, the first capacitor array 221 will store a voltage of (VREF−VAN), and the second capacitor array 222 will store a voltage of (VREF−VAP).
Please refer to FIG. 4, which illustrates another circuit of the prior art bit value determination unit of FIG. 2 formed in a voltage comparison stage. As illustrated in FIG. 4, when in the voltage comparison stage, the switch unit 210 is switched off; the first capacitor array 221 has a first equivalent capacitor with a capacitance of KC and a second equivalent capacitor with a capacitance of (2N−K)C; the second capacitor array 222 has a third equivalent capacitor with a capacitance of KC and a fourth equivalent capacitor with a capacitance of (2N−K)C, wherein, both K and N are positive integers, K=1 to 2N−1; the bias contact of the first equivalent capacitor is coupled to VREF; the bias contact of the second equivalent capacitor is coupled to VGND; the bias contact of the third equivalent capacitor is coupled to VGND; the bias contact of the fourth equivalent capacitor is coupled to VREF.
During the voltage comparison stage, the comparator 230 will see a voltage of VREF−VAN+(K/2N)VREF at the positive input end, and a voltage of VREF−VAP+(1−K/2N)VREF at the negative input end, i.e., a voltage difference of VAP−VAN−(1−K/2N)VREF between the positive input end and the negative input end. Taking N=4 as an example, wherein:
when K=1, the voltage difference will be VAP−VAN−(⅞)VREF;
when K=2, the voltage difference will be VAP−VAN−(¾)VREF;
when K=3, the voltage difference will be VAP−VAN−(⅝)VREF;
when K=4, the voltage difference will be VAP−VAN−(½)VREF;
when K=5, the voltage difference will be VAP−VAN−(⅜)VREF;
when K=6, the voltage difference will be VAP−VAN−(¼)VREF;
when K=7, the voltage difference will be VAP−VAN−(⅛)VREF;
when K=8, the voltage difference will be VAP−VAN−0;
when K=9, the voltage difference will be VAP−VAN−(−⅛)VREF;
when K=10, the voltage difference will be VAP−VAN−(−¼)VREF;
when K=11, the voltage difference will be VAP−VAN−(−⅜)VREF;
when K=12, the voltage difference will be VAP−VAN−(−½)VREF;
when K=13, the voltage difference will be VAP−VAN−(−⅝)VREF;
when K=14, the voltage difference will be VAP−VAN−(−¾)VREF;
when K=15, the voltage difference will be VAP−VAN−(−⅞)VREF.
During the voltage comparison stage, K is initially set at 8 to compare VAP−VAN with 0, and if VAP−VAN is higher than 0, K will be changed to 4 to compare VAP−VAN with (½)VREF, and if VAP−VAN is lower than (½)VREF, K will be changed to 6 to compare VAP−VAN with (¼)VREF, and so forth. When K=8, (the first equivalent capacitor, the second equivalent capacitor) will form a combination of (8C, 8C); when K=4, (the first equivalent capacitor, the second equivalent capacitor) will form a combination of (4C, 12C); and when K=6, (the first equivalent capacitor, the second equivalent capacitor) will form a combination of (6C, 10C).
Therefore, assume VAP−VAN=( 9/32)VREF, then the comparator 230 will output “1” when K is initially set at 8—because ( 9/32)VREF−0 is higher than 0, and K will then be changed to 4; when K is at 4, the comparator 230 will output “0”—because ( 9/32)VREF−(½)VREF is lower than 0, and K will then be changed to 6; when K is at 6, the comparator 230 will output “1”—because ( 9/32)VREF−(¼)VREF is higher than 0, and K will then be changed to 5; when K is at 5, the comparator 230 will output “0”—because ( 9/32)VREF−(⅜)VREF is lower than 0. In this manner, a digital code (1010) corresponding to ( 9/32)VREF will be generated.
Besides, as there are N occurrences of dynamic energy consumption in the N bits SAR ADC during the generation of each N bits digital code, wherein the energy consumed in each occurrence of the dynamic energy consumption is equal to the product of the reference voltage VREF and the charge flowing out of the reference voltage VREF, therefore, given a specified value of the reference voltage VREF, the charge flowing out of the reference voltage VREF has to be reduced to minimize the dynamic energy consumption in the SAR ADC. According to the architecture of the prior art SAR ADC, the only way to reducing the dynamic energy consumption therein seems to be reducing the basic capacitance C. However, reducing the basic capacitance C can deteriorate SNR (Signal to Noise Ratio), and thereby impact the resolution of the analog to digital conversion of the SAR ADC.
In view of the foregoing problem, a novel SAR analog to digital conversion architecture is needed to reduce the dynamic energy consumption without sacrificing SNR.